The present invention relates generally to a frequency generator for generating a digital signal and, in particular, to a digital clock frequency doubler that doubles the frequency of a digital clock signal.
Clock frequency doublers are widely used in integrated circuits. Several applications make use of phase locked loops (PLLs) to double the frequency of an input clock. However, PLLs require a high design effort and time for implementation. Further, they consume large silicon area and may require external components for usage, resulting in an increased cost.
Other clock frequency doubler designs require an input clock with exactly 50% duty cycle, which is difficult to attain in a chip. Further, they are implemented with analog circuits and are not suitable for input clocks having low frequencies. Designs with analog implementations require large silicon area.